1. Field of the Invention
The present invention relates to a quadrature amplitude modulation (QAM) digital radio communication system, and more particularly, to an interference detection circuit in a demodulation circuit thereof.
2. Description of the Related Art
Recently, in a QAM digital radio communication system, a so-called single frequency transit system is adopted, thus simplifying the hardware of the system. This will be explained later in detail.
In the single frequency transit system, however, since there are various kinds of interference included in a desired signal, an interference detection circuit is provided to compensate for the interference without increasing the number taps of a transversal equalizer circuit.
A prior art interference detection circuit is constructed by a comparator which monitors all the tap coefficients used for the transversal equalizer circuit. As a result, one of the tap coefficients having a maximum value is detected so as to indicate a center of each interference signal. This also will be explained later in detail.
In the above-mentioned prior art interference detection circuit, however, if the phase of each interference signal is deviated, the tap coefficients fluctuate, so that it is impossible to accurately indicate the center of each interference signal.
It is an object of the present invention to provide a QAM signal demodulation circuit having an improved interference detection circuit capable of accurately indicating the center of each interference signal.
According to the present invention, in a QAM signal demodulation circuit including first and second delay circuits for receiving an I-axis component and an Q-axis component of a baseband signal, a tap coefficient calculating circuit for calculating first tap coefficients in accordance with the delayed I-axis component and second tap coefficients in accordance with the delayed Q-axis component, an interference detection circuit, for detecting a center of an interference signal included in the baseband signal, a control circuit for controlling delay time periods of the first and second delay circuits in accordance with an output signal of the interference detection circuit, first and second transversal equalizers for equalizing the I-axis component and the Q-axis component in accordance with the first and second tap coefficients, and an adder for adding the output signals the first and second transversal equalizers, the interference detection circuit is constructed by a plurality of absolute value adders, each for adding an absolute value of one of the first tap coefficients and one of the second tap coefficients having the same timing, and a comparator for comparing output values of the absolute value adders with each other.